1. Technical Field
The present invention relates generally to the field of data transmission and more particularly to circuits for on-chip AC coupling, stable common-mode voltage generation and baseline wander compensation for high-speed receivers. The invention can provide a full suite AC coupling solution including AC coupling, common mode generation, and baseline wander compensation. The solution can be fully integrated, meaning it is all on-chip, does not require any off-chip components, and meets the stringent requirements of preceding a DFE based high-speed transceiver.
2. Description of the Related Art
In high-speed transceiver design, AC coupling in the channel between the transmitter and the receiver connection is typically preferred and is often required for the functioning of the transmission link. This is particularly true for decision feedback equalization (DFE) based receivers. The DFE receiver operates as a nonlinear equalizer, and is effective to recover data that have been severely damaged by channel loss, reflections and high-frequency crosstalk. Such receivers are particularly useful in high speed backplane transceivers of 6 Gbps and beyond, especially for challenging applications that involve long-range legacy channels. A DFE receiver functions by subtracting the inter-symbol interference (ISI) arising from previously detected data from data that is being currently received. A receiver of this type is susceptible to noise and fluctuations in the DC and low frequency contents of the signal. AC coupling is an effective way of removing the ineluctable common-mode voltage mismatch and the low frequency disturbance. Such coupling insulates the DFE receiver from the channel, and allows for separate receiver common-mode voltage optimization from the transmitter.
One phenomenon that is a problem in an AC coupled system is baseline wander (BLW), which is signal dependent and varies over time. BLW affects the low frequency contents of the received signal and can cause errors in the detected data. The baseline wander is even more severe for an on-chip AC coupled system. This is due to the high AC coupling corner frequency resulting from the small devices that can be afforded on-chip.
The BLW in an on-chip AC coupled system must be mitigated for reliable link functioning. In the prior art, baseline wander compensation can be partitioned into the following major categories: DSP (digital signal processing) based; adaptive equalizer based; peak-detector based; and quantized feedback methods.
Digital BLW compensators, exemplified by U.S. Pat. No. 6,415,003, cancel baseline wander effects in the digital domain. The entire signal processing including the BLW compensation and the equalization are done by DSP algorithms. A high-resolution ADC is required to detect the tiny BLW change over time. This type of compensator is not practical for multi-Gbps transceivers using current CMOS technology, due to the unrealistic simultaneous requirements of ultra high-speed and high-resolution ADC.
The adaptive equalizer based BLW compensator, exemplified by U.S. Pat. No. 6,047,026, treats the baseline wander as a common source of ISI, and uses adaptive FIR or IIR filters to cancel BLW. For the FIR case, this type of compensator would require a large number of filter taps, that may be on the order of thousands, to track the tiny slowly varying baseline change. One solution to this problem is to use an IIR unit inside the DFE FIR filter to deal with the BLW. However, the BLW correction interacts and brings difficulty to the DFE adaptation loop. Both methods are not suitable for high-speed transceivers because of associated cost or interference.
The peak-detector based BLW compensators, exemplified by U.S. Pat. No. 5,940,442, are based on the assumption that the baseline wander is the dominating source of error. The amount of baseline wander is controlled by detecting the peak pulse against a predetermined threshold voltage, and subtracting the low-pass filtered version of the pulse. The scheme works well on equalized data. But when large amount of channel-limiting ISI coexist, the nonlinearly subtracted feedback peak-currents includes both the BLW and the channel-limiting ISI information. As a result, the ISI can not be linearly passed to the next stage, and is permanently damaged for DFE. These compensators are not suitable for our application.
Quantized feedback theory for baseline wander compensation is well known and is exemplified by U.S. Pat. No. 5,699,386. However, previous arts in this category are limited to simple circuits, wherein little signal processing is done between the AC coupling corner and the quantization device. Critical circuit issues such as stable common-mode voltage maintenance, mitigation of high-frequency feed-through from the quantized feedback, and prevention of excess current and capacitive loading from the baseline restoration circuit are not addressed.
When implementing a BLW correction circuit in the signal path before a DFE receiver, a number of design considerations preclude the use of existing methods such as those referred to above. These design considerations include the following:
1) A well defined common-mode voltage is needed before the DFE. The common-mode voltage has fundamental impact on the key performance measures of an analog circuitry, including linearity, bandwidth, signal-swing and many others. The DFE functions only when the transistors are biased in the saturation region. The common-mode voltage (Vcm) has to be stable, to guarantee consistent performance and maintain the dynamic range.
2) The clock feed-through or kick-back noise from the BLW correction circuit to the high-speed signal path needs to be mitigated. This is even more critical if DFE is used. If unprotected, the high frequency noise appears as jitter and distortion, and damages the data for proper DFE.
3) The current loading to the high-pass filter output node has to be well controlled. In a high-speed SERDES, the clock is recovered from the received data. The high-pass filter corner frequency has to be sufficiently low in order to pass through enough information to set up the timing loop before the BLW loop setup. The high-pass transfer function is given by Hhp(s)=sRC/(1+sRC). With a limited size capacitor available on the chip, the equivalent impedance R has to be large to maintain the corner frequency.
4) The capacitive loading must be minimized, because of the difficult return-loss and bandwidth requirement at multi-Gbps high data rate. The total parasitic budget drops quickly with the increase of the transmission rate. At 6.4 Gb/s, even with the favorite exact resistive matching, it is far from comfortable to accommodate all the essential elements without damage returnloss performance. Zero additional capacitive loading is the prerequisite of BLWC for 6.4 Gb/s+ transceivers. It is desirable for the capacitive loading from the BLW correction circuitry to be exempt from the high-speed signal path.
In view of the above, it would be desirable to offer a complete integrated AC coupling solution for applications of both DC balanced and non-DC balanced transmission. It would also be beneficial to provide a better technique for BLW correction that does not impose clock feed-through to the high-speed data path, and does not add extra capacitive or resistive loading. Moreover, it would be desirable to offer on-chip common-mode voltage generation and maintenance that is not dependent on gain, temperature or other IC process variations.